t_id
1537
t_cpu
i386
t_adddate
2005/03/25
t_result
0
t_knownrunerror
0
t_opts
-Ogr
Record count: 50
Total = 50
OK=4 Percentage= 8.00
Skipped=46 Percentage= 92.00
Result type | Cat. | Count | Percentage | First date | Last Date |
Successfully run | 4 | 8.0 | 2024/09/26 19:54:00 70 | 2024/09/26 22:38:00 79 | |
i386 | 4 | 100.0 | 2024/09/26 19:54:00 70 | 2024/09/26 22:38:00 79 | |
go32v2 | 4 | 100.0 | 2024/09/26 19:54:00 70 | 2024/09/26 22:38:00 79 | |
3.3.1 | 4 | 100.0 | 2024/09/26 19:54:00 70 | 2024/09/26 22:38:00 79 | |
Skipping test because for other cpu | 46 | 92.0 | 2024/09/26 18:42:00 90 | 2024/09/26 23:02:00 44 | |
powerpc | 14 | 30.4 | 2024/09/26 19:41:00 35 | 2024/09/26 23:02:00 44 | |
powerpc64 | 17 | 37.0 | 2024/09/26 18:42:00 90 | 2024/09/26 22:29:00 103 | |
wasm32 | 7 | 15.2 | 2024/09/26 19:31:00 339 | 2024/09/26 22:50:00 299 | |
riscv64 | 8 | 17.4 | 2024/09/26 19:14:00 123 | 2024/09/26 19:59:00 123 | |
linux | 39 | 84.8 | 2024/09/26 18:42:00 90 | 2024/09/26 23:02:00 44 | |
wasi | 7 | 15.2 | 2024/09/26 19:31:00 339 | 2024/09/26 22:50:00 299 | |
3.3.1 | 30 | 65.2 | 2024/09/26 18:42:00 90 | 2024/09/26 22:50:00 299 | |
3.2.3 | 16 | 34.8 | 2024/09/26 21:17:00 71 | 2024/09/26 23:02:00 44 |
{ %cpu=i386 } { %opt=-Ogr } {$mode delphi} type my_rec = record my_field: string; end; var my_fyl: my_rec; my_str: array[0..99] of char; function my_func(var f: my_rec):PChar; begin my_func:=@my_str[1]; end; procedure my_proc(var f: my_rec; const s: String); var i, len: Integer; wascur: PChar; begin len := length(s); wascur := my_func(f); for i:=0 to len-1 do wascur[i]:=s[i+1]; end; begin my_proc(my_fyl,'xxx'); my_str[0]:='y'; writeln(my_str); end. { It's a spilling bug: # [23] wascur[i]:=s[i+1]; movl -8(%ebp),%ireg23d # Register %ireg24d allocated movl %ireg16d,%ireg24d incl %ireg24d # Register %ireg24d released # Register %ireg25d allocated movl %ireg24d,%ireg25d # Register %ireg26d allocated movl -12(%ebp),%ireg26d # Register %ireg26d released # Register %edi allocated leal (%ireg26d,%ireg16d,1),%edi # Register %ireg23d,%ireg25d released becomes # [23] wascur[i]:=s[i+1]; movl -8(%ebp),%edx # Register %ecx allocated movl -20(%ebp),%ecx incl %ecx # Register %eax allocated movl -12(%ebp),%eax # Register %eax released # Register %edi,%eax allocated movl -20(%ebp),%eax # Register %eax released leal (%eax,%eax,1),%edi # Register %edx,%ecx released ireg16d is spilled to -20(%ebp), so before the leal it must be loaded into a register. The spilling code picks eax, but that one is already used at that moment (by ireg26d). }