11.3 Optimization switches

This is where the various optimizing switches and their actions are described, grouped per switch.

-On: 

with n = 1..3: these switches activate the optimizer. A higher level automatically includes all lower levels.

• Level 1 (-O1) activates the peephole optimizer (common instruction sequences are replaced by faster equivalents).
• Level 2 (-O2) enables the assembler data flow analyzer, which allows the common subexpression elimination procedure to remove unnecessary reloads of registers with values they already contain.
• Level 3 (-O3) equals level 2 optimizations plus some time-intensive optimizations.

-OG: 

This causes the code generator (and optimizer, IF activated), to favor faster, but code-wise larger, instruction sequences (such as ”subl $4,%esp”) instead of slower, smaller instructions (”enter $4”). This is the default setting.

-Og: 

This one is exactly the reverse of -OG, and as such these switches are mutually exclusive: enabling one will disable the other.

-Or: 

This setting causes the code generator to check which variables are used most, so it can keep those in a register.

-Opn: 

with n = 1..3: Setting the target processor does NOT activate the optimizer. It merely influences the code generator and, if activated, the optimizer:

• During the code generation process, this setting is used to decide whether a jump table or a sequence of successive jumps provides the best performance in a case statement.
• The peephole optimizer takes a number of decisions based on this setting, for example it translates certain complex instructions, such as
  movzbl (mem), %eax|

  to a combination of simpler instructions

  xorl %eax, %eax  
  movb (mem), %al

  for the Pentium.

-Ou: 

This enables uncertain optimizations. You cannot use these always, however. The previous section explains when they can be used, and when they cannot be used.